1. Field of the Invention
The present invention relates generally to semiconductors and, more particularly, to semiconductor fabrication methods for improving critical dimensions in metal film stacks.
2. Description of Related Art
Metal film stacks are employed in integrated circuits to connect lower elements lying below an interconnect structure to upper elements lying above the metal film stacks. For example, FIG. 2B illustrates two prior-art metal film stacks in the form of a left metal film stack 126 and a right metal film stack 127 that connect to, respectively, left and right conducting plugs 15 and 16 in an interconnect structure 5. Lower elements (not shown) may be located below the interconnect structure 5, and upper elements (likewise not shown) may be located above the metal film stacks 126 and 127. During fabrication, a registration error exceeding a critical dimension in a photolithographic process may result in misalignment of the metal film stacks with the conducting elements (e.g., via plugs) in such an interconnect structure, thereby adversely affecting or even destroying functionality of a portion of the integrated circuit. Typical constructions of such prior-art metal film stacks 126 and 127, such as illustrated in FIGS. 2B, 3B, 4 and 5, further may have resistivities ranging from about 0.05 ohms per square (Ω/sq) to about 0.5 Ω/sq.